"); //-->
module vga(
VGA_R,
VGA_G,
VGA_B,
VGA_H_SYNC,
VGA_V_SYNC,
VGA_SYNC,
VGA_BLANK,
CCD_MCLK,
iCLK,
iRST_N );
parameter H_SYNC_CYC = 96;
parameter H_SYNC_BACK = 45+3;
parameter H_SYNC_ACT = 640; // 646
parameter H_SYNC_FRONT= 13+3;
parameter H_SYNC_TOTAL= 800;
// Virtical Parameter ( Line )
parameter V_SYNC_CYC = 2;
parameter V_SYNC_BACK = 30+2;
parameter V_SYNC_ACT = 480; // 484
parameter V_SYNC_FRONT= 9+2;
parameter V_SYNC_TOTAL= 525;
// Start Offset
parameter X_START = H_SYNC_CYC+H_SYNC_BACK;
parameter Y_START = V_SYNC_CYC+V_SYNC_BACK;
output [9:0] VGA_R;
output [9:0] VGA_G;
output [9:0] VGA_B;
output reg VGA_H_SYNC;
output reg VGA_V_SYNC;
output VGA_SYNC;
output VGA_BLANK;
output reg CCD_MCLK;
input iCLK;
input iRST_N;
reg [9:0] H_Cont;
reg [9:0] V_Cont;
always @(posedge iCLK)
begin
CCD_MCLK <= ~CCD_MCLK;
end
assign VGA_BLANK = VGA_H_SYNC & VGA_V_SYNC;
assign VGA_SYNC = 1'b0;
wire [9:0] OVGA_R,OVGA_G,OVGA_B;
assign OVGA_R = 10'b0000011111;
assign OVGA_B = 10'b0000110110;
assign OVGA_G = 10'b0001100001;
assign VGA_R = ( H_Cont>=X_START && H_Cont<X_START+H_SYNC_ACT &&
V_Cont>=Y_START && V_Cont<Y_START+V_SYNC_ACT )
? OVGA_R : 0;
assign VGA_G = ( H_Cont>=X_START && H_Cont<X_START+H_SYNC_ACT &&
V_Cont>=Y_START && V_Cont<Y_START+V_SYNC_ACT )
? OVGA_G : 0;
assign VGA_B = ( H_Cont>=X_START && H_Cont<X_START+H_SYNC_ACT &&
V_Cont>=Y_START && V_Cont<Y_START+V_SYNC_ACT )
always@(posedge iCLK or negedge iRST_N)
begin
if(!iRST_N)
begin
H_Cont <= 0;
VGA_H_SYNC <= 0;
end
else
begin
if( H_Cont < H_SYNC_TOTAL )
H_Cont <= H_Cont+1;
else
H_Cont <= 0;
if( H_Cont < H_SYNC_CYC )
VGA_H_SYNC <= 0;
else
VGA_H_SYNC <= 1;
end
end
always@(posedge iCLK or negedge iRST_N)
begin
if(!iRST_N)
begin
V_Cont <= 0;
VGA_V_SYNC <= 0;
end
else
begin
if(H_Cont==0)
begin
if( V_Cont < V_SYNC_TOTAL )
V_Cont <= V_Cont+1;
else
V_Cont <= 0;
if( V_Cont < V_SYNC_CYC )
VGA_V_SYNC <= 0;
else
VGA_V_SYNC <= 1;
end
end
end
endmodule
*博客内容为网友个人发布,仅代表博主个人观点,如有侵权请联系工作人员删除。